On the receiving (RX) side of a Peripheral Component Interconnect (PCI such as PCI Express PCI Express or PCIe) serial bus expansion bus controller, there are posted transaction layer packet (TLP) buffer and completion TLP buffer in a store and forward architecture. The receive buffers (RX buffers such as the receive buffers in a transaction layer of a PCIe endpoint) facilitate error filtering and flow control of TLPs. Identification (ID) based ordering is a feature in PCIe where a completion TLP may pass a posted TLP if the posted TLP's requester ID is different from the completion TLP's completer ID, even if the posted and completion TLPs are associated with the same Virtual Channel (VC). This ordering requirement between completion TLP and posted TLPs requires tracking the order of reception of the posted TLPs and the completion TLPs from the PCIe link as well as the respective identifications (IDs) and virtual channel (VC) IDs of the posted and completion TLPs.
These requirements are further complicated by the fact that in a datapath architecture (e.g., a 256-bit datapath), there may be two or more TLPs coming in to a PCIe endpoint (e.g., to the receive buffers of a PCIe endpoint) during a single clock cycle or during multiple clock cycles. These two or more TLPs may be of any types and thus pose a challenge in maintaining the order of incoming posted TLPs and the completion TLPs in response to non-posted TLPs.
Therefore, there is a need for methods, systems, and computer program product for PCI implementation handing one or more packets in a single cycle or multiple clock cycles.